Process for assembling a buffer-protected halide/sulfide trilayer

The solid-state battery industry has converged on a specific architectural problem: halide electrolytes such as Li3InCl6 are chemically incompatible with high-performance sulfide electrolytes such as argyrodite (Li6PS5Cl) when placed in direct contact. The electrochemical window mismatch and interfacial side reactions that result are well-documented failure modes, and the field has broadly agreed that an oxide buffer sublayer — typically a lithium phosphate or niobate chemistry — is required to separate them. What has not been settled is how to manufacture that stack reliably, and at what buffer thickness, in a way that survives hundreds of hours of cycling without the interfacial resistance creeping to cell-killing levels. This asset directly addresses that manufacturing gap. This process patent covers the method of assembling the halide/sulfide trilayer with a buffer sublayer specified in the 0.2–3 µm thickness regime, distinguished by a concrete performance endpoint: interfacial resistance growth must remain at or below 25% over 500 hours. That endpoint is not a soft target — it is a claim limitation that ties the method to a verifiable durability outcome, giving it real enforceability against manufacturers who run the same stack but skip the thickness specification or ignore resistance-growth drift. The asset sits within Lattice Graph's solid-state battery electrolytes and interfaces portfolio as a process companion to the family's cell-architecture claims, providing manufacturing coverage that composition and device claims alone cannot reach. The strategic timing here is important. The solid-state battery supply chain is undergoing forced substitution: sulfide-only cells face thermal and chemical instability issues at the cathode side, halide-only cells face reduction instability at the anode side, and the trilayer stack is increasingly seen as the production-viable answer. As cell manufacturers move from lab-scale deposition to pilot-line and eventually gigafactory-scale manufacturing, the process recipe — specifically how thick to deposit the buffer and how to know when the stack has failed qualification — becomes the commercial battleground. A process patent that locks in a specific thickness regime and a resistance-growth endpoint is exactly the kind of manufacturing moat that licensing royalties are built on.

The trilayer architecture addressed by this process patent consists of three functional layers deposited in sequence: a Li3InCl6 halide electrolyte layer, an oxide buffer sublayer drawn from lithium phosphate (Li3PO4), lithium niobate (LiNbO3), or lithium tantalate (LiTaO3), and an argyrodite sulfide electrolyte layer. The halide provides high ionic conductivity and oxidative stability toward the cathode; the sulfide provides the reductive stability and room-temperature conductivity needed on the anode side; and the oxide buffer suppresses the direct chemical reaction between them that would otherwise produce insulating interphase products and rapidly degrade interfacial resistance. Each material class is well-characterized in isolation, but the stack behavior is determined almost entirely by the buffer sublayer — its chemistry, its morphology, and critically its thickness. The 0.2–3 µm buffer thickness regime specified in this process claim is deliberately distinct from the thinner 3–50 nm buffer regime that governs the companion cell-architecture claims. This is not an arbitrary split: the two regimes reflect fundamentally different deposition physics and different application scenarios. Sub-50 nm buffers are deposited by atomic layer deposition (ALD) or similar conformal thin-film techniques, are appropriate for laboratory-scale coin cells and pouch prototypes, and produce extremely low absolute resistance contributions. The 0.2–3 µm regime accessed by this process claim corresponds to physical vapor deposition, sputtering, or wet-chemical coating approaches that are more scalable to high-throughput manufacturing but introduce a thicker ionic-transport resistance that must be managed. The claim captures the scalable manufacturing route, not the laboratory optimum, which is precisely where the commercial value lies as production lines scale up. The computational validation for this asset is focused on the interface rather than on bulk stability of individual phases. An explicit-interface molecular dynamics simulation using the MACE machine-learning interatomic potential was run to model the Li3InCl6 / oxide buffer / argyrodite contact region at operating temperatures and under applied lithium chemical potential gradients. This simulation type — referred to internally as explicit-interface MACE-MD — is among the most computationally expensive and physically realistic tools in the Lattice Graph validation pipeline, because it does not approximate the interface as a rigid boundary but instead allows atoms on both sides to relax, diffuse, and react under thermodynamic driving forces. The simulation provides direct evidence about which buffer chemistries suppress interphase growth and which allow it, and informs the thickness-dependent resistance behavior that underlies the 25%-over-500h endpoint. Because this is a process and assembly method rather than a new crystal structure, the standard cross-potential phonon stability protocol (MACE, CHGNet, MatterSim, ORB consensus) is not applicable here — the relevant validation is interface dynamics, not bulk lattice stability, and the MACE-MD explicit-interface approach is appropriate to that question. The performance endpoint encoded in the process claim — interfacial resistance growth of 25% or less over 500 hours — was set based on coupon-level measurements of stacks assembled with buffers in the 0.2–3 µm range. This measured validation gate is the critical proof point for the claim: it establishes that the specified method, when practiced as claimed, achieves a quantified durability outcome. In practical terms, a stack that holds interfacial resistance growth below 25% over 500 hours is within the tolerance window for most automotive and consumer cell-qualification protocols, making the endpoint commercially meaningful rather than arbitrary.

The addressable market for solid-state battery manufacturing process technology sits within the broader solid-state electrolyte and cell manufacturing segment, estimated at $1–3 billion on a technology-licensing and royalty basis as production volumes scale from pilot to gigafactory through the late 2020s and 2030s. This estimate reflects the licensing and royalty layer on top of cell manufacturing revenue, not the full battery market, and should be treated as an order-of-magnitude estimate given the early stage of the industry's production ramp. The denominator that makes this a real number is the convergence of major cell manufacturers — Toyota, Samsung SDI, Solid Power, QuantumScape, and their Tier 1 automotive supply-chain partners — on trilayer or multi-electrolyte architectures as the production-viable path for the next generation of cells. The buyers of this kind of process IP are cell manufacturers and their electrolyte material suppliers. A cell manufacturer who has independently arrived at the halide/sulfide trilayer architecture must navigate the existing process patent landscape before committing capital to a production line. A process claim that covers the 0.2–3 µm buffer thickness regime and specifies a resistance-growth endpoint creates a licensing conversation at exactly the moment the manufacturer is finalizing their deposition process recipe — which is also the moment they are least able to pivot to a different architecture. Royalty logic for a process patent in this space typically follows a per-cell or per-kWh basis, with rates negotiated as a percentage of the incremental manufacturing cost attributable to the buffer deposition step. Given that the buffer sublayer deposition is a discrete, attributable process step, this makes royalty calculation relatively straightforward compared to composition claims that are harder to trace through a finished cell. There is also a licensing angle toward equipment manufacturers: companies building ALD, sputtering, or wet-coating tools optimized for the 0.2–3 µm oxide buffer regime have an interest in validating that their equipment produces stacks within the claim's performance envelope, as that validation supports their own sales cycle to cell manufacturers. Cross-licensing arrangements with equipment OEMs represent a secondary revenue channel beyond direct cell-manufacturer royalties.

process moat with a thickness-keyed carve-out

0.2-3 um buffer sublayer + dR_int endpoint distinguishes published Li3InCl6+phosphate/niobate process art

The primary acquirers or licensees for this asset are cell manufacturers who are actively developing or scaling trilayer solid-state cells using halide/sulfide electrolyte combinations. The licensing conversation is most valuable at the point when a manufacturer has committed to the trilayer architecture and is finalizing their buffer deposition process recipe — typically during pilot-line buildout, before gigafactory capital commitment. At that stage, a process claim covering the manufacturer's chosen deposition regime creates leverage for a licensing arrangement that would otherwise be unavailable once the manufacturer has already made the capital investment. Toyota's solid-state battery program, Samsung SDI's sulfide cell operations, and the North American cell startups (Solid Power, Electrovaya) are all publicly committed to architectures that could intersect with this claim. Electrolyte material suppliers — particularly those selling Li3InCl6 or argyrodite powders to cell manufacturers — are secondary licensing targets, as they have a commercial interest in validating that their materials are compatible with patented assembly methods. Equipment manufacturers supplying sputtering, CVD, or wet-coating tools optimized for the 0.2–3 µm oxide buffer deposition step represent a third category of buyer or cross-licensing partner. These companies would benefit from a validated process patent as part of their equipment qualification offering to cell-manufacturer customers, and a cross-license or co-development arrangement could provide both royalty revenue and early access to production data that strengthens the claim's experimental record.

The central technical risk for this asset is that the coupon-level measurement of interfacial resistance in the 0.2–3 µm buffer regime has not yet been completed across all three recited oxide chemistries and across the full thickness range. If the experimental data, when obtained, shows that some combinations within the claimed range fail to meet the 25%-over-500h endpoint, the claim would need to be narrowed during prosecution — potentially reducing the commercial coverage. The mitigation is straightforward: run the coupon measurements as the immediate next step, prioritizing the thickness and chemistry combinations most likely to be adopted by production manufacturers (Li3PO4 and LiNbO3 at 0.5–1 µm are the most commercially probable starting points). Early data also strengthens the claim's position in any licensing negotiation, because it demonstrates that the endpoint specification is achievable and not aspirational. A secondary risk is that the prior art landscape is actively evolving: the published process art identified in FTO analysis may be joined by continuation applications or new filings that add thickness limitations or endpoint specifications, potentially narrowing the whitespace. The mitigation here is priority date — filing this claim ahead of competitor continuations establishes the priority position — combined with active monitoring of competitor prosecution in the halide/sulfide process space. The asset's role in the portfolio is as a process moat and manufacturing companion to the cell-architecture claims, not as a standalone primary asset, and its value is best realized in combination with the broader portfolio rather than in isolation.