Bandgap-graded borate and oxynitride multilayer dielectric stack for sub-2-micron packaging

Advanced semiconductor packaging is undergoing a structural transition from organic laminates to glass-core substrates, driven by the routing density, flatness, and dimensional stability that glass uniquely provides. The shift to glass enables through-glass vias (TGVs) and redistribution layers (RDL) at pitches well below two microns — territory where the conventional silicon dioxide and silicon nitride dielectric stack inherited from wafer-level processes begins to fail. Conventional SiO2/SiN offers adequate permittivity but lacks the bandgap engineering headroom to suppress carrier injection at the conductor/dielectric interface when via density and field strength increase simultaneously. The result is leakage, reliability failures, and a hard ceiling on pitch scaling. This invention addresses that ceiling directly. The claimed dielectric stack — a sequenced ladder of AlBO3, BaWO4, LiBO2, and borophosphate (BO4P) with an optional alkaline-earth silicon oxynitride cap — is architecturally organized so that bandgap increases monotonically away from the metallic conductor. The innermost layer (AlBO3) provides modest permittivity and chemical compatibility with the metal liner; the outer layers (LiBO2 at approximately 7.5 eV, BO4P at approximately 7.3 eV) present a wide-gap tunnel barrier that blocks carrier injection before leakage paths can form. The stack is designed for deposition on glass-core panels with 50–300 micron thickness, directly enabling sub-2-micron RDL pitch and TGV sidewall passivation — two of the most consequential integration challenges in next-generation high-bandwidth memory (HBM) and AI-package interconnects. The strategic timing is favorable. The glass-core packaging transition is still early-stage in its supply-chain buildout; OSATs and substrate vendors do not yet have a locked-in dielectric chemistry for sub-2-micron RDL. Filing a composition-plus-device-use patent family now plants a flag across the substitutable chemistry space — including Sr and Ca analogs of the oxynitride cap — before the industry converges on a standard. Within the integrated packaging, storage, and PFAS-treatment systems portfolio, this asset sits as a lead filing at the densest-pitch node of the glass-packaging roadmap.

Each candidate is validated by multiple independent machine-learning interatomic potentials. A material advances only when the engines agree on phonon (dynamic) stability — disagreement is surfaced, not hidden.

The core design principle is bandgap grading used as a carrier-injection suppressor rather than merely as a leakage-reduction measure. Starting from the conductor interface and moving outward: AlBO3 serves as the liner, offering chemical stability against metal diffusion and a moderate bandgap that provides a smooth transition from the metallic Fermi level into the dielectric stack. The next layer, BaWO4, has a DFT-computed bandgap of approximately 4.73 eV — wide by oxide standards but still permitting reasonable permittivity for thin-film capacitance targets. Moving further from the conductor, LiBO2 steps up to approximately 7.47 eV, and the borophosphate BO4P sits at approximately 7.26 eV. The optional cap, Ba3Si6N4O9 (an alkaline-earth silicon oxynitride), completes the outer termination. This graded architecture means that even if localized field enhancement occurs near the conductor, the carrier must traverse an ever-higher tunneling barrier before reaching the outer passivation region — effectively distributing the energy penalty for injection across multiple interfaces rather than concentrating it at one. On the computational side, phonon stability has been assessed using MACE, one of the leading universal machine-learning interatomic potentials. The assessment confirmed the absence of imaginary phonon modes — the standard criterion for dynamic (lattice) stability — for the constituent layer materials. Static DFT calculations using a single source independently produced the bandgap values of 4.73, 7.47, and 7.26 eV for BaWO4, LiBO2, and BO4P respectively. These are band-edge values consistent with deep ultraviolet transparency and negligible thermally-activated carrier populations at typical packaging operating temperatures (up to roughly 125°C in reliability cycling). It is important to be precise about what has been modeled: the individual layer materials have been characterized computationally for their bulk phonon spectra and electronic structure. The full multilayer stack — its interface energetics, thermal expansion coefficient matching to glass, and dielectric response as an assembled heterostructure — has not been modeled in an interface molecular dynamics or DFPT simulation. That gap is the primary open validation gate. The chemistry space claimed extends beyond the primary four-component stack. The family explicitly includes Sr3Si6N4O9 and Ca3Si6N4O9 as substitutes for the Ba-bearing oxynitride cap, providing alkaline-earth tunability of the cap layer's lattice parameter and thermal expansion. This substitution space is technically motivated: the coefficient of thermal expansion (CTE) mismatch between a glass-core panel and a brittle wide-gap dielectric is a known failure mechanism in package reliability cycling. The ability to swap the alkaline-earth identity in the oxynitride cap gives process engineers a knob to tune CTE matching without abandoning the bandgap-grading architecture. For TGV passivation specifically, the geometry demands conformal sidewall coverage over via aspect ratios that can exceed 10:1 in 50-micron glass. The claimed stack's layer-by-layer structure is compatible with atomic-layer deposition (ALD) or chemical vapor deposition (CVD) of individual layers, which is mechanically necessary for conformal TGV coating. The moderate permittivity of the inner BaWO4 layer also limits parasitic capacitance on signal vias, which matters for the high-frequency (multi-GHz) signaling requirements of HBM and AI packaging interconnect.

The addressable market for advanced dielectric materials in semiconductor packaging is a derivative of the glass-core substrate and advanced OSAT market, which is estimated by industry analysts to grow from low single-digit billions to a $10 billion-plus opportunity through the early 2030s as AI accelerator and HBM packaging transitions accelerate. This estimate should be treated as an order-of-magnitude orientation rather than a precision forecast — the glass-core market in particular is in the early commercial scale-up phase and actual penetration rate depends on capital investment decisions at a small number of substrate vendors and integrated device manufacturers. The dielectric material content per panel is a fraction of total substrate value, but in advanced nodes, specialty dielectric chemistries can command meaningful royalty per wafer-equivalent area if they are IP-protected and enable otherwise-inaccessible pitch. The primary buyer profiles are glass-core substrate vendors (Corning, AGC, Schott, and the panel-based packaging entrants from Asia) and the outsourced semiconductor assembly and test (OSAT) companies building HBM and AI-package capacity — including those qualifying next-generation panel-level packaging (PLP) lines. These buyers face a common problem: their process engineers need a qualified dielectric chemistry for sub-2-micron RDL that can be deposited conformally on glass and is reliable through 85°C/85% relative humidity (85/85) and thermal cycling. A licensed or acquired IP position that comes with a computational characterization of the chemistry, a substitutable-chemistry family, and a clean freedom-to-operate reading materially reduces qualification risk relative to in-house discovery. Royalty logic for a composition-plus-device-use family in advanced packaging typically tracks either a per-panel or per-substrate-area basis. Given that dielectric stack materials are process-consumable inputs, licensing to chemical suppliers (precursor or ALD reagent suppliers such as Air Products, Entegris, Merck KGaA's semiconductor division) who supply the full stack recipe is a viable alternative to direct licensing to packaging houses. A recipe-level license converts the IP into a supply-chain position rather than a per-unit royalty, which may be commercially cleaner at the early technology stage.

bandgap-engineered ladder for sub-2-um RDL pitch with substitutable chemistries

The most strategically aligned acquirers are glass-core substrate vendors and specialty dielectric process chemistry suppliers who need to differentiate their product offerings as the glass-core packaging market grows. Substrate vendors such as Corning (through its semiconductor glass platform) or AGC have both the panel processing infrastructure and the motivation to lock in a proprietary dielectric chemistry for sub-2-micron RDL before the industry establishes a commodity standard. For them, acquiring or exclusively licensing this family creates a chemistry moat that is defensible through the duration of the patent term. Specialty chemical and ALD precursor suppliers — including Entegris, Merck KGaA's semiconductor materials division, and Air Products — could alternatively license the family as a recipe anchor, bundling precursor supply with the IP position to create a vertically integrated offering for OSAT customers. OSATs building out panel-level packaging capacity for HBM and AI interconnect (ASE, Amkor, JCET, and newer PLP entrants) are also credible licensees, particularly if they are qualifying a new glass-core substrate line and need a dielectric stack that does not conflict with existing IP held by their IDM customers. A license from Lattice Graph in advance of line qualification reduces FTO exposure and provides documented computational characterization — useful for internal process engineering teams validating the chemistry before committing ALD equipment time. The asset is most valuable to buyers who are already inside the 3–5 year window of their glass-core packaging roadmap, since that is the timescale over which the experimental validation gap can be closed in parallel with process qualification.

The most significant risk is experimental: the full multilayer stack has not been physically fabricated, and the carrier-injection suppression mechanism — while supported by the computed bandgap ladder — has not been demonstrated in a real device structure. Process integration risks are non-trivial for a four-to-five layer heterostructure on glass: inter-layer adhesion, differential thermal expansion, pinhole density in thin ALD films, and via-fill uniformity in high-aspect-ratio TGVs all require empirical qualification. The computational phonon stability result covers bulk crystalline phases; thin-film phases deposited by ALD or CVD may adopt different local structures, and the stability inference does not automatically transfer. Additionally, only one machine-learning potential (MACE) was used for phonon assessment, whereas Lattice Graph's standard consensus protocol requires agreement across multiple independent potentials — the single-potential result is suggestive but does not meet the full internal confidence threshold applied to more mature assets in the portfolio. The roadmap to de-risk follows a clear sequence. First, obtain DFT bandgap confirmation from a second independent calculation (different code or pseudopotential set) to harden the electronic structure data. Second, run interface molecular dynamics and DFPT on the two-layer heterostructures (AlBO3/BaWO4 and LiBO2/BO4P) to validate bandgap offsets and interface stability. Third, engage a university or national laboratory partner with ALD capability on glass substrates to deposit the stack and perform TEM cross-section, leakage-current, and breakdown-field measurements. Fourth, run the 85/85 and thermal-cycle reliability screens. Completing the first two steps computationally is a matter of weeks to months and materially strengthens the prosecution record; the experimental steps are the rate-limiting path and should be scoped as a collaborative program with a substrate vendor or OSAT rather than a fully internal effort.