Ordered fabrication method for integrated glass-core advanced-packaging substrates

The glass-core advanced-packaging substrates portfolio's process claim addresses one of semiconductor packaging's most consequential inflection points: the forced substitution of organic laminates by glass-core substrates as chiplet integration density outpaces what organic materials can mechanically and electrically support. Advanced packaging — heterogeneous integration of compute, memory, and analog dies at sub-10-micron pitch — demands a substrate platform with tighter dimensional tolerance, lower via-sidewall roughness, higher thermal stability, and superior dielectric properties than any organic core can provide. Glass-core substrates meet those demands, but they also introduce a new class of fabrication challenges: adhesion across dissimilar interfaces, copper via-fill reliability in high-aspect-ratio through-glass vias (TGVs), and the controlled deposition of barrier, liner, and dielectric layers in a sequence that determines final electrical and mechanical performance. This asset is a process claim — it does not claim a composition or a device, but rather the ordered sequence of deposition and formation steps that builds the integrated glass-core package stack. That framing is deliberate. Process claims in semiconductor packaging have historically proven among the most durable and most licensable categories of intellectual property, because the "what" of a structure is often independently discoverable, but the "how" — the precise ordered workflow that achieves a reliable, manufacturable result — is the operational know-how that fabs and OSATs must actually practice. Any foundry or OSAT that fabricates the integrated stack described in the parent portfolio will need to practice some form of this sequence, making the claim a process gate across the manufacturing supply chain. The timing of this filing is important. The glass-core substrate market is in early commercial ramp: Intel's Glass Core Substrate program, SHINKO and Ibiden roadmaps for glass interposers, and TSMC's advanced packaging capacity expansions are all signaling a transition that will be substantially underway within the next three to five years. Patents filed now, ahead of broad commercial adoption, establish priority that will be operative precisely when licensing conversations become commercially material.

The claimed process covers the formation and filling of through-glass vias followed by the sequential deposition of a carefully ordered layer stack: an optional aluminum nitride (AlN) or aluminum borate (AlBO3) thermal/adhesion liner; a tungsten boride (WBx) diffusion barrier; an optional tungsten-boron-nitrogen (W-B-N) compositional gradient sublayer; a copper seed layer followed by electroplated copper fill; a cap layer; redistribution-layer dielectric formation; and a high-k passive integration module. Each layer serves a distinct materials-science function, and the ordered sequence is itself the protected element — the claim is not satisfied by any arbitrary assembly of these layers, but only by their deposition in the recited order. The liner materials reflect deliberate choices rooted in interface science. AlN is a well-established wide-bandgap ceramic with high thermal conductivity (approximately 150-200 W/m·K in dense form), used here as a thermal management layer at the TGV sidewall where copper-to-glass thermal mismatch can drive delamination under thermomechanical cycling. AlBO3 offers an alternative chemistry where adhesion promotion is prioritized over bulk thermal conductivity. The WBx barrier layer is chosen for its exceptionally low copper diffusivity and high thermal stability — tungsten boride compounds suppress copper migration into the glass at temperatures encountered both during processing and in-service thermal excursions. The W-B-N gradient sublayer, when deposited, provides a compositionally graded transition that reduces interfacial stress concentration between the hard ceramic barrier and the softer copper fill, a materials engineering approach borrowed from hard-coating and cutting-tool technology but applied here to interconnect reliability. The copper fill sequence (seed plus electroplate) is standard damascene processing adapted to the high-aspect-ratio geometry of TGVs, where achieving void-free fill without seam formation requires careful control of additive chemistry and current density profiles. The cap and redistribution-layer dielectric layers close the via and define the surface wiring, while the high-k passive module integrates capacitive structures into the substrate body — a capability that removes discrete passive components from the PCB and shortens power-delivery path lengths. The integrated build referenced in the prophetic example (Example 8 in the supporting disclosure) demonstrates the full stack construction as an integrated proof vehicle, showing that the layer sequence is compatible end-to-end without introducing process conflicts such as liner cracking, copper delamination, or dielectric voiding. This prophetic example establishes a reduction-to-practice roadmap and constitutes the primary evidence of operability in the disclosure. It is honest to note that this example is prophetic rather than experimentally reduced, meaning the claim rests on the structural and chemical logic of the sequence — which is well-supported by the component-level literature for each individual layer — rather than on a fabricated, characterized physical prototype. The primary open validation gate is therefore the integrated build itself: a test vehicle fabricating the complete stack in the recited order and demonstrating that TGV fill yield, via resistance, barrier integrity, and thermal cycling reliability meet packaging qualification standards. From a materials-science perspective, the most technically differentiated element is the WBx / W-B-N gradient system at the copper-glass interface. Tungsten borides are metastable at ambient temperature but kinetically stable under the processing conditions relevant to packaging fabrication, and their diffusion-barrier performance against copper has been demonstrated in academic literature for gate-stack and interconnect applications. Applying this chemistry to glass-core TGV sidewalls is a non-obvious extension that the portfolio exploits: the combination of a hard, refractory ceramic barrier with a gradient nitrogen-doped transition layer is not a routine modification of existing copper barrier practice (which has concentrated on TaN/Ta, TiN, and Ru seed approaches in silicon via processing), and the adaptation to glass substrates — where the underlying surface chemistry and thermal expansion mismatch are fundamentally different from silicon — constitutes the core technical novelty.

The advanced packaging substrate market is experiencing a structural shift driven by the limits of transistor scaling and the imperative to integrate heterogeneous chiplets within a single package. Glass-core substrates are positioned as the next-generation platform above high-end organic substrates (coreless and build-up) for applications demanding the highest interconnect density, lowest signal loss, and best thermal dimensional stability. Industry analyst estimates place the glass substrate and glass interposer segment on a trajectory toward several billion dollars of annual revenue by the late 2020s, within a broader advanced substrate market that already exceeds $5 billion annually across high-end compute, AI accelerators, high-bandwidth memory interfaces, and RF/5G front-end modules. The figure cited in the portfolio context is a $5 billion-plus addressable market — this should be understood as an estimate of the advanced substrate segment broadly rather than a precise market-research number, and the actual glass-core-specific segment will ramp more slowly as glass processing infrastructure matures. Who buys this technology? The direct commercial operators are semiconductor foundries and OSATs (outsourced semiconductor assembly and test houses) that manufacture substrate and package-level structures. Companies such as Ibiden, Shinko Electric, AT&S, Unimicron, and TTM Technologies on the substrate side, and ASE Group, Amkor, JCET, and Intel Foundry Services on the OSAT/packaging side, are the natural licensees for a process claim of this type. Fabless chip companies — AMD, NVIDIA, Qualcomm, and the major hyperscalers designing their own AI accelerators — are the ultimate demand drivers, but they typically license through their supply chains or via joint-development agreements rather than directly acquiring process IP. The licensing logic for a process claim is straightforward: any entity that builds the integrated glass-core package stack in the recited order, for commercial sale or internal consumption, is a potential licensee. Royalty structures in advanced packaging process IP typically range from 0.5% to 2% of substrate selling price, with lump-sum or milestone-based structures available for early adopters seeking freedom to operate. Given the high ASP of advanced packaging substrates (often $50-$300 per substrate depending on complexity and via count), even modest adoption rates produce meaningful royalty streams. The process claim's value also accretes if it is paired with the composition and device claims in the broader portfolio, creating a layered licensing package that covers materials, structures, and manufacturing workflow simultaneously.

process claim protecting the ordered fabrication flow

ordered deposition sequence claimed

The natural acquirers and licensees for this asset are the substrate manufacturers and OSATs that will build glass-core packages at commercial scale. On the substrate manufacturing side, Ibiden, Shinko Electric, AT&S, and Unimicron are the tier-one candidates — each is investing in next-generation substrate platforms, and a process patent that cleanly covers the integrated glass-core fabrication flow would either need to be licensed for production or acquired to block competitors. On the OSAT and integrated packaging side, ASE Group, Amkor Technology, and JCET are the most commercially active in advanced substrate integration; Intel Foundry Services, which has staked a public position on glass-core substrate technology, is a strategic buyer with both the manufacturing ambition and the IP portfolio appetite to consider acquisition. Hyperscaler in-house packaging programs — Google TPU substrate supply, Microsoft custom silicon, and Amazon Trainium/Inferentia packaging supply chains — represent a second tier of potential acquirers seeking FTO coverage for their advanced packaging sourcing. The asset's value to a buyer is highest when combined with the composition and device claims in the parent portfolio. A licensee who needs to practice the integrated stack needs freedom under all three claim types simultaneously, making the combined portfolio materially more valuable than any single family in isolation. A buyer acquiring the process family alone obtains a blocking position on the manufacturing workflow, which is useful but limited; a buyer acquiring the integrated portfolio obtains control of the material, the structure, and the process — a comprehensive position across the glass-core advanced packaging stack that would be difficult and expensive for competitors to design around.

The primary risk for this asset is the prophetic status of the integrated build. Patent claims supported by prophetic examples are legally valid, but they carry more vulnerability to enablement challenges than claims backed by experimental data. If a competitor challenges the claim in inter partes review or litigation, the burden will be on the portfolio owner to demonstrate that a person of ordinary skill in the art could practice the full ordered sequence without undue experimentation. The individual layers are well-characterized in the literature, and the ordered sequence is logically justified by materials-science reasoning, but the combination has not yet been physically assembled and characterized as a complete stack. Completing the integrated build — even a limited test vehicle — before the patent is granted or before commercial licensing conversations begin would substantially de-risk this exposure. The roadmap to address it is clear: partner with a university cleanroom or a commercial packaging R&D center to fabricate a TGV glass coupon, deposit the layer sequence, and run a basic characterization suite. A secondary risk is claim scope during prosecution. The ordered-sequence element is a strength in litigation (hard to design around) but may also invite prior-art rejections based on partial sequences in the literature — for example, AlN liners in silicon TGV processes or WBx barriers in gate-stack applications. A well-managed prosecution strategy that distinguishes the glass-core context and the specific combination of all elements in the recited order, rather than arguing individual layer novelty, is the correct response. Continuation applications preserving priority while broadening or narrowing claims in response to examiner art should be planned proactively as the commercial landscape develops.