Lattice Graph × Intel

Lattice Graph is a computational materials-discovery platform built around a knowledge graph spanning millions of compositions. At its core is a multi-validator pipeline: every candidate material must earn consensus across multiple independent machine-learning interatomic potentials — MACE, CHGNet, MatterSim, and ORB — before any DFT compute is allocated, and phonon and thermodynamic stability are required checkpoints, not optional analyses. This architecture eliminates the single-model false-positive problem that plagues conventional virtual screening and means only genuinely stable, manufacturable compositions advance to targeted simulation. Beyond stability validation, the platform runs targeted property simulations — dielectric permittivity, thermal conductivity, diffusion barriers, bandgap, and more — tuned to the specific physics each program demands. A freedom-to-operate and patent-whitespace engine screens across more than 300,000 materials patents at composition and claim level, surfacing clear IP paths before any fabrication investment. The knowledge graph also carries a large atlas of labeled negative results from failed experiments, giving probabilistic models the failure-mode signal that published literature systematically omits and making the platform's predictions meaningfully better calibrated than anything trained on positive-only data.

Intel's glass-core substrate roadmap is one of the most materials-intensive transitions in advanced packaging in a generation. EMIB-plus-glass-core integration samples are targeted around early 2026, with broader adoption expected before 2030 — a compressed window in which the via liner, copper diffusion barrier, redistribution-layer dielectric, and overall stack architecture need to be locked in with defensible IP before process recipes solidify. Lattice Graph's computational discovery platform was built precisely for this problem: multi-potential consensus validation on the phonon and thermodynamic stability of thin-film candidates, followed by targeted simulation of the thermal, diffusion, and dielectric properties that govern whether a material survives in a through-glass via or an RDL stack at production scale. Intel's parallel work on high-k and wide-gap dielectrics for logic gate stacks and MIM capacitors adds a second computational dimension. Gate-stack and MIM integration requires materials that simultaneously maximize permittivity, maintain wide bandgap for leakage control, and survive aggressive thermal budgets — a three-way trade-off where conventional trial-and-error is slow and expensive. Our knowledge graph covers the layered-perovskite and Ruddlesden-Popper composition spaces that are most promising for this application, with stability and permittivity data already validated against DFT. The combination of Intel's glass-core roadmap timeline, its HBM-era packaging needs, and its gate-stack dielectric programs maps cleanly onto four of our discovery portfolios. Our freedom-to-operate screening across 300,000-plus materials patents means Intel can identify deposition-ready compositions with clear IP paths before the architecture locks in — not after, when design-arounds are expensive or impossible.

Intel's glass-core substrate roadmap is one of the most materials-intensive transitions in advanced packaging in a generation. EMIB-plus-glass-core integration samples are targeted around early 2026, with broader adoption expected before 2030 — a compressed window in which the via liner, copper diffusion barrier, redistribution-layer dielectric, and overall stack architecture need to be locked in with defensible IP before process recipes solidify. Lattice Graph's computational discovery platform was built precisely for this problem: multi-potential consensus validation on the phonon and thermodynamic stability of thin-film candidates, followed by targeted simulation of the thermal, diffusion, and dielectric properties that govern whether a material survives in a through-glass via or an RDL stack at production scale. Intel's parallel work on high-k and wide-gap dielectrics for logic gate stacks and MIM capacitors adds a second computational dimension. Gate-stack and MIM integration requires materials that simultaneously maximize permittivity, maintain wide bandgap for leakage control, and survive aggressive thermal budgets — a three-way trade-off where conventional trial-and-error is slow and expensive. Our knowledge graph covers the layered-perovskite and Ruddlesden-Popper composition spaces that are most promising for this application, with stability and permittivity data already validated against DFT. The combination of Intel's glass-core roadmap timeline, its HBM-era packaging needs, and its gate-stack dielectric programs maps cleanly onto four of our discovery portfolios. Our freedom-to-operate screening across 300,000-plus materials patents means Intel can identify deposition-ready compositions with clear IP paths before the architecture locks in — not after, when design-arounds are expensive or impossible.

The Glass-core advanced-packaging substrates portfolio is the primary match for Intel's substrate roadmap. It covers the through-glass via liner, copper diffusion barrier, redistribution-layer dielectric, and cap layers as an integrated, teardown-verifiable stack — each layer qualified against package reliability endpoints. With EMIB-plus-glass-core samples in view around early 2026, the window to establish clean IP positions on via-wall materials is now, not after process integration reviews. The Integrated packaging, storage and PFAS-treatment systems portfolio extends this coverage to integrated glass-core substrate stack claims and to the high-k passive layers that appear in advanced packaging as embedded MIM capacitors. The Ba2HfO4 Ruddlesden-Popper dielectric in this portfolio is directly relevant to Intel's DRAM and packaging capacitor programs, delivering a permittivity around 53.5 with wide bandgap for leakage control. The Dielectric, ferroelectric and wide-bandgap oxides portfolio addresses Intel's logic and memory gate-stack and MIM integration needs — high-k materials that survive aggressive thermal budgets without sacrificing leakage performance. Finally, the High-power thermal-interface materials portfolio is relevant to Intel's data-center and AI accelerator packages, where thermal-interface resistance at the die-to-lid and lid-to-heat-spreader interfaces is a first-order power-density constraint. All four portfolios carry freedom-to-operate-clean or narrow-gap positions established before the broader industry has populated the adjacent claim space.

The Lattice Graph web application gives materials and packaging teams an interactive workspace for navigating the knowledge graph, reviewing multi-potential validation results, and running targeted property simulations on candidate compositions without writing code. Teams working on Intel's through-glass via stack can filter candidates by thermal conductivity, diffusion-barrier performance, or ALD/CVD process compatibility, compare stability evidence across MACE, CHGNet, MatterSim, and ORB simultaneously, and export simulation reports tied to specific package reliability endpoints. The application also surfaces the freedom-to-operate and patent-whitespace screening results directly alongside property data, so a process engineer evaluating a new via liner composition sees both the thermal performance projection and the IP landscape in a single view. Collaboration features let packaging integration, process development, and IP teams share annotated composition sets and simulation workspaces — useful for Intel's cross-functional glass-core substrate development process, where materials decisions involve process, reliability, and legal stakeholders simultaneously.

A typical engagement begins with a scoped composition-space survey: we ingest Intel's target specifications — via geometry, thermal budget, deposition process constraints, reliability endpoints — and run the multi-potential stability pipeline across the relevant composition neighborhoods, delivering a ranked candidate set with stability evidence, targeted property simulations, and initial freedom-to-operate signals within four to six weeks. This deliverable is designed to plug into Intel's integration review process as a materials input, not a research output. From there, engagements typically expand into either a portfolio licensing discussion around specific assets — with pricing structured around field-of-use and exclusivity — or a continuous-access arrangement covering the Knowledge-Graph and freedom-to-operate APIs plus application seats for the process, integration, and IP teams. Custom simulation campaigns targeting Intel's specific process conditions, such as ALD sequence validation for the tungsten boride barrier or permittivity modeling at Intel's MIM stack thermal budgets, can be scoped as add-on workstreams. Engagement structure is flexible; most semiconductor customers begin with a time-boxed asset evaluation tied to a specific program milestone.