Lattice Graph × Samsung Electro-Mechanics

Lattice Graph is a computational materials-discovery platform built around a knowledge graph that spans millions of compositions and their thermodynamic, mechanical, and electronic properties. Every candidate material is stress-tested by multiple independent machine-learning interatomic potentials — MACE, CHGNet, MatterSim, and ORB — and must reach consensus on phonon and thermodynamic stability before advancing, with density functional theory calculations used as the final arbiter. That multi-validator consensus dramatically reduces the number of physically implausible candidates that would otherwise consume wet-lab time. On top of that stability engine, the platform runs targeted simulations scoped to a specific application — via-liner thermal resistance, dielectric permittivity and leakage current, copper diffusion kinetics — so the output handed to process engineers is not a generic materials list but a narrowed set of candidates already ranked against the metric that matters for the program. A freedom-to-operate screening layer cross-references every candidate against more than 300,000 materials patents, mapping composition-level and claim-level whitespace so R&D teams know before they synthesize whether a new material sits in clear IP territory or needs a design-around. The platform also carries a large atlas of labeled negative results — failed experiments from prior discovery cycles — so the model learns from what did not work, not only from published successes.

Samsung Electro-Mechanics sits at the intersection of two of the most demanding materials problems in the semiconductor supply chain simultaneously: building a glass-core advanced-packaging platform in Sejong in time for interposer production around 2028, and sustaining a leading position in multilayer ceramic capacitor dielectrics that depends on finding higher-permittivity oxide formulations before competitors do. These are not adjacent problems that share a common customer — they are distinct physics challenges that require separate material classes, separate deposition windows, and separate intellectual property strategies. Lattice Graph has portfolios that address both lines, already computationally validated and screened for a clear IP path. The Sejong glass-substrate pilot has a hard timeline. A glass-core stack needs a via-wall liner that handles the mismatch in coefficient of thermal expansion, a copper diffusion barrier thin enough to preserve the geometric budget in high-aspect-ratio through-glass vias, and an RDL dielectric that can survive sub-2-micron pitch redistribution-layer processing. Each of those layers has its own failure mode, its own patent density, and its own process integration constraint. Lattice Graph has computationally validated candidates for each layer — from an aluminum nitride thermal liner that cuts through-via thermal resistance by more than half, to a refractory tungsten boride barrier that blocks copper diffusion at sub-TaN thickness, to a bandgap-graded borate/oxynitride dielectric ladder designed for sub-2-micron RDL pitch — all with freedom-to-operate status confirmed across the patent corpus. On the MLCC side, the ferroelectric and high-permittivity dielectric oxide portfolio maps directly onto the next-generation dielectric formulations Samsung Electro-Mechanics needs to extend capacitance density. The barium hafnate Ruddlesden-Popper phase, for instance, delivers a permittivity around 53.5 with a wide bandgap for leakage suppression — the combination that matters for high-density MIM capacitors and for the embedded passive layers in the glass-core stack itself. Because both business lines share an underlying need for dielectric oxides with tunable permittivity and good thermal stability, the same discovery campaign reaches both programs.

Samsung Electro-Mechanics sits at the intersection of two of the most demanding materials problems in the semiconductor supply chain simultaneously: building a glass-core advanced-packaging platform in Sejong in time for interposer production around 2028, and sustaining a leading position in multilayer ceramic capacitor dielectrics that depends on finding higher-permittivity oxide formulations before competitors do. These are not adjacent problems that share a common customer — they are distinct physics challenges that require separate material classes, separate deposition windows, and separate intellectual property strategies. Lattice Graph has portfolios that address both lines, already computationally validated and screened for a clear IP path. The Sejong glass-substrate pilot has a hard timeline. A glass-core stack needs a via-wall liner that handles the mismatch in coefficient of thermal expansion, a copper diffusion barrier thin enough to preserve the geometric budget in high-aspect-ratio through-glass vias, and an RDL dielectric that can survive sub-2-micron pitch redistribution-layer processing. Each of those layers has its own failure mode, its own patent density, and its own process integration constraint. Lattice Graph has computationally validated candidates for each layer — from an aluminum nitride thermal liner that cuts through-via thermal resistance by more than half, to a refractory tungsten boride barrier that blocks copper diffusion at sub-TaN thickness, to a bandgap-graded borate/oxynitride dielectric ladder designed for sub-2-micron RDL pitch — all with freedom-to-operate status confirmed across the patent corpus. On the MLCC side, the ferroelectric and high-permittivity dielectric oxide portfolio maps directly onto the next-generation dielectric formulations Samsung Electro-Mechanics needs to extend capacitance density. The barium hafnate Ruddlesden-Popper phase, for instance, delivers a permittivity around 53.5 with a wide bandgap for leakage suppression — the combination that matters for high-density MIM capacitors and for the embedded passive layers in the glass-core stack itself. Because both business lines share an underlying need for dielectric oxides with tunable permittivity and good thermal stability, the same discovery campaign reaches both programs.

The Glass-core advanced-packaging substrates portfolio is the most direct match for the Sejong pilot. It covers the full ordered stack — thermal liner, copper barrier, dielectric, cap, and passive layers — with each layer computationally verified against package reliability endpoints and screened for a clear IP path. The materials in this portfolio were selected specifically for the geometry and process temperatures of through-glass via integration, making them deposition-ready candidates rather than academic starting points. The process method claims covering the ordered deposition sequence are included, which matters for protecting the manufacturing flow as much as protecting the materials themselves. The Integrated packaging, storage and PFAS-treatment systems portfolio provides the RDL dielectric and high-k passive layer candidates that complete the glass-core stack, along with the barium hafnate high-permittivity dielectric that bridges over to the MLCC program. The bandgap-graded multilayer dielectric stack in this portfolio targets sub-2-micron RDL pitch specifically, which aligns with the resolution requirements of the interposer routing layers Samsung Electro-Mechanics is engineering toward 2028. The Dielectric, ferroelectric and wide-bandgap oxides portfolio addresses the MLCC dielectric business directly. High-permittivity oxide formulations validated by the multi-potential consensus engine and ranked by permittivity, leakage current, and thermal stability give the MLCC dielectric team a prioritized candidate list ahead of synthesis. The High-power thermal-interface materials portfolio rounds out the package integration picture, relevant to the thermal management demands that arise when high-bandwidth memory and logic are co-integrated on a glass interposer at the power densities Samsung Electro-Mechanics targets.

The Lattice Graph platform application gives materials and process teams a structured workspace for running multi-stage discovery campaigns. Teams configure a composition search scoped to a specific application constraint — via thermal resistance, dielectric permittivity range, copper diffusion coefficient — and the platform runs each candidate through the multi-potential stability consensus before surfacing results. The workflow is designed so that process engineers who are not computational scientists can read the outputs: stability verdicts, ranked property predictions, and freedom-to-operate status are presented alongside deposition-relevant parameters rather than raw ab initio numbers. For a team managing both the Sejong glass-substrate program and the MLCC dielectric roadmap, the project workspace allows separate discovery campaigns to run in parallel with shared access to the underlying knowledge graph, so findings from the dielectric oxide campaign can be cross-applied to the embedded passive layer requirements in the glass-core stack without duplicating effort. The negative-result atlas surfaces automatically when a candidate fails a stability filter, showing prior failed compositions in the same neighborhood so the team understands why the model is routing around a particular stoichiometry rather than simply returning a null result.

A typical engagement begins with a scoping session in which Lattice Graph maps the specific application constraints — via geometry, deposition temperature window, target permittivity range, reliability endpoints — onto the relevant portfolios and knowledge-graph query parameters. Within two to four weeks, the platform delivers a ranked candidate report covering composition, stability consensus, key property predictions, and freedom-to-operate status for each candidate in the shortlist. That report is structured for handoff to a synthesis team, not for further computational iteration, and it includes the negative-result context needed to understand which adjacent compositions were ruled out and why. For Samsung Electro-Mechanics, a natural engagement structure covers the Sejong glass-core stack and the MLCC dielectric program as parallel workstreams that share access to the dielectric oxide knowledge-graph layer. Licensing options range from a targeted portfolio license covering a specific asset set to a broader platform access arrangement that includes ongoing knowledge-graph API queries and freedom-to-operate screening for new compositions as process integration work surfaces new candidates. Pricing is structured around the number of programs and the depth of API access, and initial scoping sessions carry no commitment.